Logical effort using particle swarm optimization algorithm-an examination on the 8-stage full adder circuit
The delay reduction of logic architecture leads to the reduction in costs associated with the development time, fabrication (chip area), and power requirements, as well as increased performance. The logical effort technique provides an easy way to compare and select circuit topologies, choose the be...
| Published in: | Proceedings - CSPA 2010: 2010 6th International Colloquium on Signal Processing and Its Applications |
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| Main Author: | |
| Format: | Conference paper |
| Language: | English |
| Published: |
2010
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| Online Access: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-77956534011&doi=10.1109%2fCSPA.2010.5545228&partnerID=40&md5=b086b588e07a5a948e26a9dbf46bebc5 |