Resource-Efficient 64-bit Karatsuba Multiplier using LUTs and DSP slices

• Published in: 2024 IEEE 14TH SYMPOSIUM ON COMPUTER APPLICATIONS & INDUSTRIAL ELECTRONICS, ISCAIE 2024
• Main Authors: Hashim, Shakirah; Mansor, Nur Farraliza
• Format: Proceedings Paper
• Language: English
• Published: IEEE 2024
• Subjects: Computer Science; Engineering
• Online Access: https://www-webofscience-com.uitm.idm.oclc.org/wos/woscc/full-record/WOS:001283898700003

Modem Field Programmable Gate Array (FPGA) is now equipped with Digital Signal Processing (DSP) block for faster computation. This feature can be exploited to speed-up the multiplication process which is widely needed during encryption. However, the operand size of DSP multipliers are asymmetric, 24 x 17 bits, thus complicates the multiplication process. As DSP has high-throughput function, it must be optimally used to avoid resource waste. Thus, 64-bit Karatsuba multiplier is proposed in this paper to exploit the DSP advancement, based on two optimizations: operand decomposition and operand arrangement. Both optimizations are tailored to the DSP asymmetric multiplier architecture. The proposed design is implemented on Kintex 7. We only utilized 8 DSP slices and several slices of LUTs resource, smaller than non-standard tiling Karatsuba. In fact, we achieved higher DSP efficiency (97.6%) as each DSP slice is optimally utilized.