Resource-Efficient 64-bit Karatsuba Multiplier using LUTs and DSP slices
Modem Field Programmable Gate Array (FPGA) is now equipped with Digital Signal Processing (DSP) block for faster computation. This feature can be exploited to speed-up the multiplication process which is widely needed during encryption. However, the operand size of DSP multipliers are asymmetric, 24...
| 出版年: | 2024 IEEE 14TH SYMPOSIUM ON COMPUTER APPLICATIONS & INDUSTRIAL ELECTRONICS, ISCAIE 2024 |
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| 主要な著者: | , , |
| フォーマット: | Proceedings Paper |
| 言語: | English |
| 出版事項: |
IEEE
2024
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| 主題: | |
| オンライン･アクセス: | https://www-webofscience-com.uitm.idm.oclc.org/wos/woscc/full-record/WOS:001283898700003 |