Effect of gate dielectric to the threshold voltage of 65 nm NMOS structure

• 出版年: AIP Conference Proceedings
• 第一著者: 2-s2.0-70450250488
• フォーマット: Conference paper
• 言語: English
• 出版事項: 2009
• オンライン･アクセス: https://www.scopus.com/inward/record.uri?eid=2-s2.0-70450250488&doi=10.1063%2f1.3160209&partnerID=40&md5=b855d4a09e0f871859423c1f4e7de128
• ISSN: 15517616
• DOI: 10.1063/1.3160209

With the intention of approaching to a technology of 65 nm, many parameters were changed as a step to fabricate the device. The gate oxide thickness was one of the parameters that have been observed. In this project, Silvaco TCA D tools were used to find the optimum value of threshold voltage for 65 nm technology nMOS transistor. The silicon dioxide (SiO2) was used to growth the gate oxide by adjusted the time and temperature of the oxidation process. The thickness of gate oxide was varied from 30Å to 100 Å and the results were tabulated and observed. As the gate oxide thickness increase, the value of threshold voltage was increased. By using Silvaco TCAD Tools, the results show that the optimum value of threshold voltage is 0.26 V. The value is in the range with ITRS guideline for 65 nm device. © 2009 American Institute of Physics.