| Summary: | This project focuses on five different gate lengths; 0.35 μm, 0.25 μm, 0.18 μm, 0.13 μm and 0.09μm. These gate lengths were determined by changing the etch location of polysilicon during the fabrication process of NMOS. The electrical characteristics that investigated were threshold voltage (V th) and current maximum (Id max). The investigation process was performed by analyzing boron doping concentration in the plysilicon doping, altering impurity in polysilicon doping and also changing arsenic doping concentration in source/drain annealing. The doping concentration was varied properly to gain an optimum property of the transistor. SILVACO TCAD tools were used to obtain electrical characteristics of NMOS structure. In summary, smaller gate length 0.09μm have optimum voltage and highest current compared to others with Vth=0.0225 V and Id max= 972.465μA for device performance. © 2009 American Institute of Physics.
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