| Summary: | Negative/Positive Bias Temperature Instability (N / PBTI) is one of the most important readability issues due to aggressive technology scaling. The transistor performance will degrade and eventually reduce the performance of the circuit. As SRAM is a widely used circuit in microprocessors, it is important to understand the impact of BTI on the stability of SRAM. In this research, the read and write operation of the SRAM circuit will be evaluated based on the delay and average power, and threshold voltage will be analysed for device-level analysis. The simulation work is conducted by using the HSPICE MOSRA model, and the 16 n m Predictive Technology Model (PTM) is used to design the SRAM. The percentage of average power due to NBTI is higher by 10.36 % as compared to PBTI. The average power due to Nit being higher by 14.5% as compared to the Nit-Not defect mechanism. It can be concluded that the voltage threshold and average power are more affected by NBTI compared to PBTI. © 2024 IEEE.
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