An FPGA implementation of shift converter block technique on FIFO for RS232 to universal serial bus converter

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An FPGA implementation of shift converter block technique on FIFO for RS232 to universal serial bus converter

To meet the standard modern system communication demands, the paper represents the implementation of bidirectional shift converter technique for the embedded converter RS232 to Universal Serial Bus circuit block within FPGA using Verilog HDL language to be applied in a system wireless communication...

書誌詳細
出版年:	Proceedings - 2012 IEEE Control and System Graduate Research Colloquium, ICSGRC 2012
第一著者:	2-s2.0-84867366860
フォーマット:	Conference paper
言語:	English
出版事項:	2012
オンライン･アクセス:	https://www.scopus.com/inward/record.uri?eid=2-s2.0-84867366860&doi=10.1109%2fICSGRC.2012.6287165&partnerID=40&md5=28c6d0a83ed8365c13911b6d0cf2d803

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