Design of CMOS Programmable Gain Amplifier for Reconfigurable System

• Published in: 2024 IEEE International Conference on Applied Electronics and Engineering, ICAEE 2024
• Main Author: Ramli N.S.; Razak A.H.A.; Halim A.K.; Md Idros M.F.; Mohd Hassan S.L.; Al Junid S.A.M.; Chee S.P.
• Format: Conference paper
• Language: English
• Published: Institute of Electrical and Electronics Engineers Inc. 2024
• Online Access: https://www.scopus.com/inward/record.uri?eid=2-s2.0-85204809482&doi=10.1109%2fICAEE62924.2024.10667620&partnerID=40&md5=ed180325c6d8d07337436c9ac1a4879f

This paper presents the design of a 130 nm CMOS programmable gain amplifier (PGA) designed for reconfigurable systems. The primary objective is to analyse the gain range of the amplifier, which is programmable for various applications, including biological signal processing, intermediate frequency (IF), radio frequency (RF), and low voltage operations. The PGA circuit is designed and simulated using 130 nm Silterra technology in Mentor Graphics software. With a single 1.5 V supply, measured results for a 2-bit digital signal implementation demonstrate that the gain range of the amplifier is adjustable for different applications. The average power consumption of the PGA is 120.61 μW. The CMOS PGA is designed to offer substantial power gain with minimal power consumption trade-offs, making it highly suitable for reconfigurable system applications. © 2024 IEEE.