| Summary: | In wearable devices, a less complex power management unit (PMU) circuit that delivers supply voltage steadily is desired due to its small form factor. In PMU, low dropout regulator (LDO) is one of the important parts that delivers a stable supply voltage. Therefore, in this project a stable, high PSRR and minimal LDO circuit architecture is proposed. A conventional PMOS type pass transistor circuit is considered due to small quiescent current and less complexity circuit where no additional circuitry and less area required. The error amplifier (EA) and pass device element of LDO circuits uses a dual stage differential amplifier architecture method to achieve a relatively high gain and stability. RC Miller compensation circuit has also been adopted to improve its stability. The proposed LDO has been designed and simulated using CMOS 45nm process technology in cadence analog design environment. The simulation result shows that, it regulates an output voltage at 1.6V from a 1.8V supply, with a minimum dropout voltage of 200mV using a reference voltage of 1V. The proposed design successfully achieves a stable system with gain of 38dB and phase margin of 68.57° and PSRR of 50.85dB at 1KHz. © 2024 IEEE.
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