Optimization of a Current-Starved Ring-Based Voltage Controlled Oscillator (VCO) for High-Frequency Band Phase Locked Loop (PLL) using 45nm CMOS Technology
In this paper, we optimize a Current-Starved Ring Voltage-Controlled Oscillator (VCO) using 45nm CMOS technology, specifically for high-frequency band Phase-Locked Loops (PLLs). With 45nm CMOS technology, simulations were performed with Cadence Virtuoso to see how modifications affected the performa...
| Published in: | 2024 IEEE International Conference on Applied Electronics and Engineering, ICAEE 2024 |
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| Format: | Conference paper |
| Language: | English |
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Institute of Electrical and Electronics Engineers Inc.
2024
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| Online Access: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85204803677&doi=10.1109%2fICAEE62924.2024.10667618&partnerID=40&md5=8414e7775c7c17e8efd5de80b793111c |
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2-s2.0-85204803677 Sallah S.S.M.; Azulyzal A.I.H.; Noorsal E.; Rashid A.N.A.; Ahmed A.S.A. Optimization of a Current-Starved Ring-Based Voltage Controlled Oscillator (VCO) for High-Frequency Band Phase Locked Loop (PLL) using 45nm CMOS Technology 2024 2024 IEEE International Conference on Applied Electronics and Engineering, ICAEE 2024 10.1109/ICAEE62924.2024.10667618 https://www.scopus.com/inward/record.uri?eid=2-s2.0-85204803677&doi=10.1109%2fICAEE62924.2024.10667618&partnerID=40&md5=8414e7775c7c17e8efd5de80b793111c In this paper, we optimize a Current-Starved Ring Voltage-Controlled Oscillator (VCO) using 45nm CMOS technology, specifically for high-frequency band Phase-Locked Loops (PLLs). With 45nm CMOS technology, simulations were performed with Cadence Virtuoso to see how modifications affected the performance of a three-stage single-ended ring oscillator circuit. The analysis examined power consumption, frequency, and phase noise while accounting for variations in transistor sizes (lengths of 0.13μm, 0.2μm, and 0.4μm). A measurement of 0.13 μm in length and width produced the best outcome. The power supply voltage was fixed at 1.5Volts, while the control voltage (Vcontrol) was changed between 0.1 and 0.6 Volts. This allowed the frequency tuning range to be 9.94 to 10.25GHz. When measuring phase noise at a 1MHz offset, the results showed that the power consumption was 120.7μW at 0.6V of Vcontrol, and the value of phase noise was -81.7dBc/Hz. These results show how this optimized VCO design can be used in high-frequency PLL applications, helping to improve the stability and efficiency of signal processing in cutting-edge telecommunications systems. © 2024 IEEE. Institute of Electrical and Electronics Engineers Inc. English Conference paper |
| author |
Sallah S.S.M.; Azulyzal A.I.H.; Noorsal E.; Rashid A.N.A.; Ahmed A.S.A. |
| spellingShingle |
Sallah S.S.M.; Azulyzal A.I.H.; Noorsal E.; Rashid A.N.A.; Ahmed A.S.A. Optimization of a Current-Starved Ring-Based Voltage Controlled Oscillator (VCO) for High-Frequency Band Phase Locked Loop (PLL) using 45nm CMOS Technology |
| author_facet |
Sallah S.S.M.; Azulyzal A.I.H.; Noorsal E.; Rashid A.N.A.; Ahmed A.S.A. |
| author_sort |
Sallah S.S.M.; Azulyzal A.I.H.; Noorsal E.; Rashid A.N.A.; Ahmed A.S.A. |
| title |
Optimization of a Current-Starved Ring-Based Voltage Controlled Oscillator (VCO) for High-Frequency Band Phase Locked Loop (PLL) using 45nm CMOS Technology |
| title_short |
Optimization of a Current-Starved Ring-Based Voltage Controlled Oscillator (VCO) for High-Frequency Band Phase Locked Loop (PLL) using 45nm CMOS Technology |
| title_full |
Optimization of a Current-Starved Ring-Based Voltage Controlled Oscillator (VCO) for High-Frequency Band Phase Locked Loop (PLL) using 45nm CMOS Technology |
| title_fullStr |
Optimization of a Current-Starved Ring-Based Voltage Controlled Oscillator (VCO) for High-Frequency Band Phase Locked Loop (PLL) using 45nm CMOS Technology |
| title_full_unstemmed |
Optimization of a Current-Starved Ring-Based Voltage Controlled Oscillator (VCO) for High-Frequency Band Phase Locked Loop (PLL) using 45nm CMOS Technology |
| title_sort |
Optimization of a Current-Starved Ring-Based Voltage Controlled Oscillator (VCO) for High-Frequency Band Phase Locked Loop (PLL) using 45nm CMOS Technology |
| publishDate |
2024 |
| container_title |
2024 IEEE International Conference on Applied Electronics and Engineering, ICAEE 2024 |
| container_volume |
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| container_issue |
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| doi_str_mv |
10.1109/ICAEE62924.2024.10667618 |
| url |
https://www.scopus.com/inward/record.uri?eid=2-s2.0-85204803677&doi=10.1109%2fICAEE62924.2024.10667618&partnerID=40&md5=8414e7775c7c17e8efd5de80b793111c |
| description |
In this paper, we optimize a Current-Starved Ring Voltage-Controlled Oscillator (VCO) using 45nm CMOS technology, specifically for high-frequency band Phase-Locked Loops (PLLs). With 45nm CMOS technology, simulations were performed with Cadence Virtuoso to see how modifications affected the performance of a three-stage single-ended ring oscillator circuit. The analysis examined power consumption, frequency, and phase noise while accounting for variations in transistor sizes (lengths of 0.13μm, 0.2μm, and 0.4μm). A measurement of 0.13 μm in length and width produced the best outcome. The power supply voltage was fixed at 1.5Volts, while the control voltage (Vcontrol) was changed between 0.1 and 0.6 Volts. This allowed the frequency tuning range to be 9.94 to 10.25GHz. When measuring phase noise at a 1MHz offset, the results showed that the power consumption was 120.7μW at 0.6V of Vcontrol, and the value of phase noise was -81.7dBc/Hz. These results show how this optimized VCO design can be used in high-frequency PLL applications, helping to improve the stability and efficiency of signal processing in cutting-edge telecommunications systems. © 2024 IEEE. |
| publisher |
Institute of Electrical and Electronics Engineers Inc. |
| issn |
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| language |
English |
| format |
Conference paper |
| accesstype |
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| record_format |
scopus |
| collection |
Scopus |
| _version_ |
1812871795498287104 |