| Summary: | In this paper, we optimize a Current-Starved Ring Voltage-Controlled Oscillator (VCO) using 45nm CMOS technology, specifically for high-frequency band Phase-Locked Loops (PLLs). With 45nm CMOS technology, simulations were performed with Cadence Virtuoso to see how modifications affected the performance of a three-stage single-ended ring oscillator circuit. The analysis examined power consumption, frequency, and phase noise while accounting for variations in transistor sizes (lengths of 0.13μm, 0.2μm, and 0.4μm). A measurement of 0.13 μm in length and width produced the best outcome. The power supply voltage was fixed at 1.5Volts, while the control voltage (Vcontrol) was changed between 0.1 and 0.6 Volts. This allowed the frequency tuning range to be 9.94 to 10.25GHz. When measuring phase noise at a 1MHz offset, the results showed that the power consumption was 120.7μW at 0.6V of Vcontrol, and the value of phase noise was -81.7dBc/Hz. These results show how this optimized VCO design can be used in high-frequency PLL applications, helping to improve the stability and efficiency of signal processing in cutting-edge telecommunications systems. © 2024 IEEE.
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