Design and Analysis of Single Master Multiple Slave Serial Peripheral Interface (SPI) on FPGA

• Published in: 2024 IEEE International Conference on Applied Electronics and Engineering, ICAEE 2024
• Main Author: Rahimi A.H.; Halim A.K.; Razak A.H.A.; Idros M.F.M.; Osman F.N.; Junid S.A.M.A.; Hassan S.L.M.
• Format: Conference paper
• Language: English
• Published: Institute of Electrical and Electronics Engineers Inc. 2024
• Online Access: https://www.scopus.com/inward/record.uri?eid=2-s2.0-85204778067&doi=10.1109%2fICAEE62924.2024.10667616&partnerID=40&md5=651f98205d85fb047b7f707051499421

This paper presents the design and analysis of an FPGA-based Single Master Multiple Slave Serial Peripheral Interface (SPI) system. SPI is a peripheral interface used to facilitate communication between devices. It performs data transfer by designating master and slave devices. However, current peripheral interfacing protocols have certain limitations. Parallel communication requires extensive wiring and is susceptible to noise and crosstalk, while serial communication can sometimes consume more power, have slower transfer speeds, and exhibit lower throughput. The main objective of this study is to design an SPI module capable of operating in both single-slave and multiple-slave modes. Simulations were performed using Modelsim to verify the functionality. Subsequently, the designs were successfully implemented on an FPGA. In conclusion, the single master multiple slave SPI module was successfully designed and verified. © 2024 IEEE.