Investigation of a 130nm CMOS Low Noise Amplifier's Performance Across Corner Conditions for WLAN Applications

• Published in: 14th IEEE Symposium on Computer Applications and Industrial Electronics, ISCAIE 2024
• Main Author: Nu'man Azman A.H.; Muhamad M.; Amin N.H.; Hussin H.; Aziz A.A.; Ahmad N.
• Format: Conference paper
• Language: English
• Published: Institute of Electrical and Electronics Engineers Inc. 2024
• Online Access: https://www.scopus.com/inward/record.uri?eid=2-s2.0-85198905201&doi=10.1109%2fISCAIE61308.2024.10576348&partnerID=40&md5=e3a76f178480fd9530fdfec8a206274b

Wireless communication systems depend on Low Noise Amplifiers (LNAs) to ensure smooth connectivity and high data throughput. However, manufacturing variability, encompassing slight fluctuations in process parameters, voltage, and temperature, can significantly impact LNA performance. This study scrutinizes the performance of a 130nm CMOS LNA operating at 2.4GHz, intended for WLAN applications, under various corner conditions such as transistor speed, resistor, and capacitor variations. Leveraging Silterra's 0.13 μm RFMOS process technology and Cadence software, the LNA was designed, with corner conditions drawn from the model library. Results at 2.4GHz reveal that the FF transistor condition demonstrates superior performance, boasting a 22.91 % higher gain, 16.81 % lower noise figure, and 44.68% lower Third Order Input Intercept Point compared to the LNA's SS conditions. During the resistor-capacitor study, the LNA exhibits commendable performance under Capacitance TT - Maximum Resistance and FF transistor settings but underperforms under Maximum Capacitance - Minimum Resistance and SS transistor conditions. This thorough evaluation of the LNA's performance under various corner conditions provides valuable insights for optimizing its real-world manufacturing performance. © 2024 IEEE.