Resource-Efficient 64-Bit Karatsuba Multiplier using LUTs and DSP Slices
Modern Field Programmable Gate Array (FPGA) is now equipped with Digital Signal Processing (DSP) block for faster computation. This feature can be exploited to speed-up the multiplication process which is widely needed during encryption. However, the operand size of DSP multipliers are asymmetric, 2...
Published in: | 14th IEEE Symposium on Computer Applications and Industrial Electronics, ISCAIE 2024 |
---|---|
Main Author: | Hashim S.; Mansor N.F. |
Format: | Conference paper |
Language: | English |
Published: |
Institute of Electrical and Electronics Engineers Inc.
2024
|
Online Access: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85198902424&doi=10.1109%2fISCAIE61308.2024.10576219&partnerID=40&md5=2173db62d0ea10aeca3838a1ae9ae7c7 |
Similar Items
-
Integer Based Fully Homomorphic DSP Accelerator using Weighted-Number Theoretic Transform
by: Hashim S.; Benaissa M.
Published: (2023) -
Design and Implementation of 3-bit Calculator for an ALU using Vertical and Crosswise Multiplication
by: Rasappan S.; Thangavel G.; Rafeek Ahmed S.; Ahamed Nishath S.; Ali M.A.M.; Tahir N.M.
Published: (2023) -
A security analysis of Iot encryption: Sidechannel cube attack on Simeck32/64
by: Buja A.G.; Abdul-Latip S.F.; Ahmad R.
Published: (2018) -
Multiplying Tensile Strength of RTV Silicone Rubber via Fiberglass & Kevlar Plies Reinforcement
by: Mahmood S.S.; Shayuti M.S.M.; Othman N.H.; Husin H.; Sharudin R.W.; Alias N.H.; Marpani F.
Published: (2023) -
Design and analysis of 8-bit Smith Waterman based DNA sequence alignment accelerator's core on ASIC design flow
by: Halim A.K.; Majid Z.A.; Mansor M.A.; Al Junid S.A.M.; Mohamed S.; Khairudin N.; Yassin A.I.M.; Idros M.F.; Hassan S.L.M.
Published: (2010)