Resource-Efficient 64-Bit Karatsuba Multiplier using LUTs and DSP Slices
Modern Field Programmable Gate Array (FPGA) is now equipped with Digital Signal Processing (DSP) block for faster computation. This feature can be exploited to speed-up the multiplication process which is widely needed during encryption. However, the operand size of DSP multipliers are asymmetric, 2...
| Published in: | 14th IEEE Symposium on Computer Applications and Industrial Electronics, ISCAIE 2024 |
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| Main Author: | |
| Format: | Conference paper |
| Language: | English |
| Published: |
Institute of Electrical and Electronics Engineers Inc.
2024
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| Online Access: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85198902424&doi=10.1109%2fISCAIE61308.2024.10576219&partnerID=40&md5=2173db62d0ea10aeca3838a1ae9ae7c7 |