Resource-Efficient 64-Bit Karatsuba Multiplier using LUTs and DSP Slices
Modern Field Programmable Gate Array (FPGA) is now equipped with Digital Signal Processing (DSP) block for faster computation. This feature can be exploited to speed-up the multiplication process which is widely needed during encryption. However, the operand size of DSP multipliers are asymmetric, 2...
Published in: | 14th IEEE Symposium on Computer Applications and Industrial Electronics, ISCAIE 2024 |
---|---|
Main Author: | |
Format: | Conference paper |
Language: | English |
Published: |
Institute of Electrical and Electronics Engineers Inc.
2024
|
Online Access: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85198902424&doi=10.1109%2fISCAIE61308.2024.10576219&partnerID=40&md5=2173db62d0ea10aeca3838a1ae9ae7c7 |
id |
2-s2.0-85198902424 |
---|---|
spelling |
2-s2.0-85198902424 Hashim S.; Mansor N.F. Resource-Efficient 64-Bit Karatsuba Multiplier using LUTs and DSP Slices 2024 14th IEEE Symposium on Computer Applications and Industrial Electronics, ISCAIE 2024 10.1109/ISCAIE61308.2024.10576219 https://www.scopus.com/inward/record.uri?eid=2-s2.0-85198902424&doi=10.1109%2fISCAIE61308.2024.10576219&partnerID=40&md5=2173db62d0ea10aeca3838a1ae9ae7c7 Modern Field Programmable Gate Array (FPGA) is now equipped with Digital Signal Processing (DSP) block for faster computation. This feature can be exploited to speed-up the multiplication process which is widely needed during encryption. However, the operand size of DSP multipliers are asymmetric, 24 x 17 bits, thus complicates the multiplication process. As DSP has high-throughput function, it must be optimally used to avoid resource waste. Thus, 64-bit Karatsuba multiplier is proposed in this paper to exploit the DSP advancement, based on two optimizations: operand decomposition and operand arrangement. Both optimizations are tailored to the DSP asymmetric multiplier architecture. The proposed design is implemented on Kintex 7. We only utilized 8 DSP slices and several slices of LUTs resource, smaller than non-standard tiling Karatsuba. In fact, we achieved higher DSP efficiency (97.6%) as each DSP slice is optimally utilized. © 2024 IEEE. Institute of Electrical and Electronics Engineers Inc. English Conference paper |
author |
Hashim S.; Mansor N.F. |
spellingShingle |
Hashim S.; Mansor N.F. Resource-Efficient 64-Bit Karatsuba Multiplier using LUTs and DSP Slices |
author_facet |
Hashim S.; Mansor N.F. |
author_sort |
Hashim S.; Mansor N.F. |
title |
Resource-Efficient 64-Bit Karatsuba Multiplier using LUTs and DSP Slices |
title_short |
Resource-Efficient 64-Bit Karatsuba Multiplier using LUTs and DSP Slices |
title_full |
Resource-Efficient 64-Bit Karatsuba Multiplier using LUTs and DSP Slices |
title_fullStr |
Resource-Efficient 64-Bit Karatsuba Multiplier using LUTs and DSP Slices |
title_full_unstemmed |
Resource-Efficient 64-Bit Karatsuba Multiplier using LUTs and DSP Slices |
title_sort |
Resource-Efficient 64-Bit Karatsuba Multiplier using LUTs and DSP Slices |
publishDate |
2024 |
container_title |
14th IEEE Symposium on Computer Applications and Industrial Electronics, ISCAIE 2024 |
container_volume |
|
container_issue |
|
doi_str_mv |
10.1109/ISCAIE61308.2024.10576219 |
url |
https://www.scopus.com/inward/record.uri?eid=2-s2.0-85198902424&doi=10.1109%2fISCAIE61308.2024.10576219&partnerID=40&md5=2173db62d0ea10aeca3838a1ae9ae7c7 |
description |
Modern Field Programmable Gate Array (FPGA) is now equipped with Digital Signal Processing (DSP) block for faster computation. This feature can be exploited to speed-up the multiplication process which is widely needed during encryption. However, the operand size of DSP multipliers are asymmetric, 24 x 17 bits, thus complicates the multiplication process. As DSP has high-throughput function, it must be optimally used to avoid resource waste. Thus, 64-bit Karatsuba multiplier is proposed in this paper to exploit the DSP advancement, based on two optimizations: operand decomposition and operand arrangement. Both optimizations are tailored to the DSP asymmetric multiplier architecture. The proposed design is implemented on Kintex 7. We only utilized 8 DSP slices and several slices of LUTs resource, smaller than non-standard tiling Karatsuba. In fact, we achieved higher DSP efficiency (97.6%) as each DSP slice is optimally utilized. © 2024 IEEE. |
publisher |
Institute of Electrical and Electronics Engineers Inc. |
issn |
|
language |
English |
format |
Conference paper |
accesstype |
|
record_format |
scopus |
collection |
Scopus |
_version_ |
1809678153689333760 |