Fault injection test on mitigated benchmark circuits using FPGA

• Published in: AIP Conference Proceedings
• Main Author: Subari S.F.; Rosli N.A.; Halim I.S.A.; Hassan S.L.M.; Rahim A.A.A.; Abdullah N.E.
• Format: Conference paper
• Language: English
• Published: American Institute of Physics Inc. 2024
• Online Access: https://www.scopus.com/inward/record.uri?eid=2-s2.0-85185816454&doi=10.1063%2f5.0192276&partnerID=40&md5=576b228502db72dd4fe0af0c776a7757

FPGAs (Field Programmable Gate Arrays) are integrated circuits with excellent reliability, flexibility, and capability that are widely utilized in various applications, including nuclear reactor control, aircraft, and space vehicles. However, this electronic device will perform incorrectly when exposed to high radiation, causing soft errors such as Single-Event Upset (SEU). In order to overcome this problem, redundancy is applied using the Triple Modular Redundancy (TMR) method. In this study, the fault injection test is applied to three different TMR designs using C17, B1 and Decode benchmark circuits. The tests were observed through the DE1-SoC FPGA board by comparing the output generated from a Golden Circuit (GC) and Circuit Under Test (CUT). Based on the resource utilization reports of the benchmark circuit and TMR design, Decode used 350% of logic utilization more than C17 and B1, thus showing that Decode has more area usage. For ten sets of 100 random fault injection tests, the average passes for C17, B1, and Decode is 49.4%, 50.8% and 51.6%, respectively. © 2024 Author(s).