Trade-offs and Optimization: Low Power Approaches for Area, Power Consumption, and Performance in Microprocessor Design

• Published in: Proceedings - 2023 IEEE Regional Symposium on Micro and Nanoelectronics, RSM 2023
• Main Author: Sallehuddin N.M.; Muhamad M.; Hussin H.; Halim A.K.; Wahab Y.A.
• Format: Conference paper
• Language: English
• Published: Institute of Electrical and Electronics Engineers Inc. 2023
• Online Access: https://www.scopus.com/inward/record.uri?eid=2-s2.0-85179853865&doi=10.1109%2fRSM59033.2023.10327338&partnerID=40&md5=21580c5211a5cf3e15cc27e8d6aa5c66

This research paper presents the findings of implementing low-power techniques on RISC V microprocessors using 90 nm technology. The power consumption of smaller microprocessors is a concern, despite their advantages of reduced chip size and higher operating frequency. Low-power microprocessors often involve trade-offs with size and performance constraints. The objective of this project is to apply three low-power techniques-clock gating, multi-voltage, and multi-Threshold approaches-and evaluate the resulting optimizations in timing, area, and power. The design is simulated and synthesized using Intel Quartus Prime Lite, Synopsys VCS, and Design Compiler tools. The synthesis with different compile options shows varied output values in terms of timing, area, and power consumption compared to the initial design without low-power techniques. The study concludes that setup timing slacks increase by 141%, while multi-voltage and multi-Threshold approaches significantly reduce overall power consumption and area. Clock gating demonstrates the highest optimization in timing, area, and performance and is recommended as a standalone technique. © 2023 IEEE.