Fault Tolerant Design Comparison Study of TMR and 5MR

• Published in: 2021 IEEE Symposium on Industrial Electronics and Applications, ISIEA 2021
• Main Author: Che Ismail M.M.; Abdul Halim I.S.; Mohd Hassan S.L.; Ab Rahim A.A.; Abdullah N.E.
• Format: Conference paper
• Language: English
• Published: Institute of Electrical and Electronics Engineers Inc. 2021
• Online Access: https://www.scopus.com/inward/record.uri?eid=2-s2.0-85124664081&doi=10.1109%2fISIEA51897.2021.9509996&partnerID=40&md5=e21781f43528cc424c33903780249d78

Field Programmable Gate Arrays (FPGAs) is widely used especially in critical application such as military system and aerospace system due to its reconfigurable advantages. FPGA may prone to fault due to many factors such as radiation. Redundancy method is used to overcome this problem and can improve the reliability of a system. In this work, fault tolerant design technique for Triple Modular Redundancy (TMR) and Five Modular Redundancy (5MR) were compared on DE1-SoC FPGA boards. Fault were injected by adding a fault module that made selected module become faulty to the circuit under test (CUT) board which is interfaced with the main FPGA board. The result of fault injection test shows 5MR produce more correct output than TMR even though 5MR use 1.67 times more resources. ©2021 IEEE