FPGA-BASED EDGE DETECTION TECHNIQUE WITH IMAGE FILTERS ENHANCEMENT

• Published in: 2021 IEEE Symposium on Industrial Electronics and Applications, ISIEA 2021
• Main Author: Rosli M.R.; Mohd Hassan S.L.; Abdul Halim I.S.; Abdullah N.E.; Ab Rahim A.A.
• Format: Conference paper
• Language: English
• Published: Institute of Electrical and Electronics Engineers Inc. 2021
• Online Access: https://www.scopus.com/inward/record.uri?eid=2-s2.0-85124663604&doi=10.1109%2fISIEA51897.2021.9509980&partnerID=40&md5=68dd8d111325faa25531fd073e805ad4

This paper presents field-programmable gate arrays (FPGA) based edge detection technique with image filters enhancement. Sobel operator is one of the commonly used algorithms in edge detection. The Sobel operator's issue is that the image output contains a lot of noise, which leads to missing edges of a detected object in the final processed image. Detection of edges is not reliable with only one filter present. Filters such as Gaussian, Median, Sharpening and Downsampling were proposed to remove unnecessary noise from distorting the images increase image quality, smoothness and edge visibility. Filters designed in a separate module with a particular algorithm on FPGA DE2-115 development board. These filters can be activated as single or multiple functions as desired. Using CMOS TRDB-D5M camera, edge detected real-time image displayed in 1366x768 resolution VGA monitor. Filter's output images were evaluated for the quality of smoothness and noise. Power consumption and logic elements were analyzed for efficiency. The best power consumption is using all filters without Downsampling with 347.33 mW, and the lowest total logic element design is by using the same filter combinations with 1518 total logic elements. In conclusion, edge detection works effectively at maximum brightness and a combination of all filters at the cost of higher power consumption and more logic elements used in the modules. ©2021 IEEE