Designing of input/output port based on FPGA with handshaking capability
Input/output (I/O) port is a group of interfaces that has diverse functional structures of a data processing system use to interconnect with each other. I/O port with handshaking capability is one of the powerful configurations to enable digital communication. The main intention of this project is t...
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2-s2.0-85087975050 Che Kar S.A.; Halim Z.A.; Ismail S.I.; Ismail N.; Ahmad N.; Mohamed S. Designing of input/output port based on FPGA with handshaking capability 2020 Journal of Physics: Conference Series 1529 2 10.1088/1742-6596/1529/2/022038 https://www.scopus.com/inward/record.uri?eid=2-s2.0-85087975050&doi=10.1088%2f1742-6596%2f1529%2f2%2f022038&partnerID=40&md5=794683102cb33eefe0b82599590d9d23 Input/output (I/O) port is a group of interfaces that has diverse functional structures of a data processing system use to interconnect with each other. I/O port with handshaking capability is one of the powerful configurations to enable digital communication. The main intention of this project is to design prototype of an input/output port with handshaking capability using Field Programmable Gate Array (FPGA). The main reason of using the FPGA technology is it has unlimited number reprogrammed, cuts developing cost and development time. Xilinx Foundation 2.1i Series software in VHDL description was used as a development tool in this project. The VHDL codes were assimilated into a design and development atmosphere to accomplish many subtasks such as FPGA synthesis, optimization, placement, and routing. The successful design was translated, mapped, routed, and placed onto FPGA Demo Board. XC4010XLPC84 Xilinx FPGA from XC4000XL family was used as a target board. In prototype design, the FPGA pins were connected to a parallel printer port by using a coupled 25-pin DB connector, with a 36-pin Centronics connector cable. The output signals were observed and analyzed by using a logic analyzer. © 2020 IOP Publishing Ltd. All rights reserved. Institute of Physics Publishing 17426588 English Conference paper All Open Access; Gold Open Access |
author |
Che Kar S.A.; Halim Z.A.; Ismail S.I.; Ismail N.; Ahmad N.; Mohamed S. |
spellingShingle |
Che Kar S.A.; Halim Z.A.; Ismail S.I.; Ismail N.; Ahmad N.; Mohamed S. Designing of input/output port based on FPGA with handshaking capability |
author_facet |
Che Kar S.A.; Halim Z.A.; Ismail S.I.; Ismail N.; Ahmad N.; Mohamed S. |
author_sort |
Che Kar S.A.; Halim Z.A.; Ismail S.I.; Ismail N.; Ahmad N.; Mohamed S. |
title |
Designing of input/output port based on FPGA with handshaking capability |
title_short |
Designing of input/output port based on FPGA with handshaking capability |
title_full |
Designing of input/output port based on FPGA with handshaking capability |
title_fullStr |
Designing of input/output port based on FPGA with handshaking capability |
title_full_unstemmed |
Designing of input/output port based on FPGA with handshaking capability |
title_sort |
Designing of input/output port based on FPGA with handshaking capability |
publishDate |
2020 |
container_title |
Journal of Physics: Conference Series |
container_volume |
1529 |
container_issue |
2 |
doi_str_mv |
10.1088/1742-6596/1529/2/022038 |
url |
https://www.scopus.com/inward/record.uri?eid=2-s2.0-85087975050&doi=10.1088%2f1742-6596%2f1529%2f2%2f022038&partnerID=40&md5=794683102cb33eefe0b82599590d9d23 |
description |
Input/output (I/O) port is a group of interfaces that has diverse functional structures of a data processing system use to interconnect with each other. I/O port with handshaking capability is one of the powerful configurations to enable digital communication. The main intention of this project is to design prototype of an input/output port with handshaking capability using Field Programmable Gate Array (FPGA). The main reason of using the FPGA technology is it has unlimited number reprogrammed, cuts developing cost and development time. Xilinx Foundation 2.1i Series software in VHDL description was used as a development tool in this project. The VHDL codes were assimilated into a design and development atmosphere to accomplish many subtasks such as FPGA synthesis, optimization, placement, and routing. The successful design was translated, mapped, routed, and placed onto FPGA Demo Board. XC4010XLPC84 Xilinx FPGA from XC4000XL family was used as a target board. In prototype design, the FPGA pins were connected to a parallel printer port by using a coupled 25-pin DB connector, with a 36-pin Centronics connector cable. The output signals were observed and analyzed by using a logic analyzer. © 2020 IOP Publishing Ltd. All rights reserved. |
publisher |
Institute of Physics Publishing |
issn |
17426588 |
language |
English |
format |
Conference paper |
accesstype |
All Open Access; Gold Open Access |
record_format |
scopus |
collection |
Scopus |
_version_ |
1809678481898864640 |