Junction engineering in two-stepped recessed SiGe MOSFETs for high performance application

• Published in: AIP Conference Proceedings
• Main Author: Wahab Y.A.; Soin N.; Naseer M.N.; Hussin H.; Osman R.A.M.; Johan M.R.; Hamizi N.A.; Pivehzhani O.A.; Chowdhury Z.Z.; Sagadevan S.; Sabapathy T.
• Format: Conference paper
• Language: English
• Published: American Institute of Physics Inc. 2020
• Online Access: https://www.scopus.com/inward/record.uri?eid=2-s2.0-85078152480&doi=10.1063%2f1.5142125&partnerID=40&md5=fb7cef5cac4859782c04a44b4d551bba

SiGe being one of the most diverse, emerging and richest material for MOSFETs is alluring the scientist due to its unique characteristics like high performance, high surface channel mobility and low threshold voltage as compare to that of silicon MOSFETs. In spite of so much cruciality, the performance of SiGe MOSFETs is being controlled by several factors like resistance and junction depth. These factors urged scientists to not relieve on the traditional methods of junction meteorology to utilize the actual potential and high performance of SiGe MOSFETs in terms of their application. Hence, a paradigm shift in junction engineering is being observed during last few years and discussed. The main focus of this paper is to highlight junction metrologies (ion implantation and annealing) that were tested on SiGe MOSFETs and to propose the most efficient and sustainable technique of junction engineering for high performance applications. © 2020 Author(s).