Implementation of passive functions on 0.18 μm CMOS at Ka-Band
A simplified model of microstrip line, implemented on a 0.18 μm CMOS technology at 36 GHz is presented. The technology comprises 6 metal layers and 11 layers of different substrates. The study shows that the 11-layer substrates CMOS technology can be assimilated to a single substrate with a dielectr...
| Published in: | 2016 IEEE CPMT Symposium Japan, ICSJ 2016 |
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| Main Author: | |
| Format: | Conference paper |
| Language: | English |
| Published: |
Institute of Electrical and Electronics Engineers Inc.
2016
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| Online Access: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85010637792&doi=10.1109%2fICSJ.2016.7801248&partnerID=40&md5=494a1ac1a34374c55268354275553523 |
| Summary: | A simplified model of microstrip line, implemented on a 0.18 μm CMOS technology at 36 GHz is presented. The technology comprises 6 metal layers and 11 layers of different substrates. The study shows that the 11-layer substrates CMOS technology can be assimilated to a single substrate with a dielectric constant of 4.1, having 6.9 μm of overall thickness. It is also found that, the line width that should be used to realize a 50-Ω microstrip lines is 12 um. The findings presented in this paper can accelerate the design process of microwave passive functions involving microstrip lines on such COMS technology, via the utilization circuit simulation software. © 2016 IEEE. |
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| ISSN: | |
| DOI: | 10.1109/ICSJ.2016.7801248 |