Reduction of annealed-induced wafer defects in dual-damascene copper interconnects

Reduction of annealed-induced wafer defects in dual-damascene copper interconnects

Interconnects in very large scale integration (VLSI) chips are susceptible to failure due to mechanical stress in passivated interconnect lines. These mechanisms play a collective role for intensive research of thermal stability for Cu interconnects reliability in CMOS technologies. This paper prese...

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Published in:Microelectronics Reliability
Main Author: Abdul Wahab Y.; Ahmad A.F.; Hussin H.; Soin N.
Format: Article
Language:English
Published: 2012
Online Access:https://www.scopus.com/inward/record.uri?eid=2-s2.0-84866736037&doi=10.1016%2fj.microrel.2012.07.008&partnerID=40&md5=df23c87ff96874d44e22384c15dde7f6
id 2-s2.0-84866736037
spelling 2-s2.0-84866736037
Abdul Wahab Y.; Ahmad A.F.; Hussin H.; Soin N.
Reduction of annealed-induced wafer defects in dual-damascene copper interconnects
2012
Microelectronics Reliability
52
10-Sep
10.1016/j.microrel.2012.07.008
https://www.scopus.com/inward/record.uri?eid=2-s2.0-84866736037&doi=10.1016%2fj.microrel.2012.07.008&partnerID=40&md5=df23c87ff96874d44e22384c15dde7f6
Interconnects in very large scale integration (VLSI) chips are susceptible to failure due to mechanical stress in passivated interconnect lines. These mechanisms play a collective role for intensive research of thermal stability for Cu interconnects reliability in CMOS technologies. This paper presents capabilities and performance on samples annealed using furnace vs He in situ anneal and in-line technique developed to reduce total defect count. © 2012 Elsevier Ltd. All rights reserved.

00262714
English
Article
author Abdul Wahab Y.; Ahmad A.F.; Hussin H.; Soin N.
spellingShingle Abdul Wahab Y.; Ahmad A.F.; Hussin H.; Soin N.
Reduction of annealed-induced wafer defects in dual-damascene copper interconnects
author_facet Abdul Wahab Y.; Ahmad A.F.; Hussin H.; Soin N.
author_sort Abdul Wahab Y.; Ahmad A.F.; Hussin H.; Soin N.
title Reduction of annealed-induced wafer defects in dual-damascene copper interconnects
title_short Reduction of annealed-induced wafer defects in dual-damascene copper interconnects
title_full Reduction of annealed-induced wafer defects in dual-damascene copper interconnects
title_fullStr Reduction of annealed-induced wafer defects in dual-damascene copper interconnects
title_full_unstemmed Reduction of annealed-induced wafer defects in dual-damascene copper interconnects
title_sort Reduction of annealed-induced wafer defects in dual-damascene copper interconnects
publishDate 2012
container_title Microelectronics Reliability
container_volume 52
container_issue 10-Sep
doi_str_mv 10.1016/j.microrel.2012.07.008
url https://www.scopus.com/inward/record.uri?eid=2-s2.0-84866736037&doi=10.1016%2fj.microrel.2012.07.008&partnerID=40&md5=df23c87ff96874d44e22384c15dde7f6
description Interconnects in very large scale integration (VLSI) chips are susceptible to failure due to mechanical stress in passivated interconnect lines. These mechanisms play a collective role for intensive research of thermal stability for Cu interconnects reliability in CMOS technologies. This paper presents capabilities and performance on samples annealed using furnace vs He in situ anneal and in-line technique developed to reduce total defect count. © 2012 Elsevier Ltd. All rights reserved.
publisher
issn 00262714
language English
format Article
accesstype
record_format scopus
collection Scopus
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