A 0.13μm inductively degenerated cascode CMOS LNA at 2.14GHz
A 130-nm CMOS low-noise amplifier (LNA) for WCDMA applications is presented. The circuit adopts an inductively degenerated cascode topology. A detailed methodology using power constraint noise optimization (PCNO) method that leads to an optimum width of the LNA is presented. A theoretical noise figu...
| Published in: | 2011 IEEE Symposium on Industrial Electronics and Applications, ISIEA 2011 |
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| Main Author: | |
| Format: | Conference paper |
| Language: | English |
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2011
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| Online Access: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-84855652799&doi=10.1109%2fISIEA.2011.6108680&partnerID=40&md5=21000a0032e6765b61a2cea0ea242d27 |
| Summary: | A 130-nm CMOS low-noise amplifier (LNA) for WCDMA applications is presented. The circuit adopts an inductively degenerated cascode topology. A detailed methodology using power constraint noise optimization (PCNO) method that leads to an optimum width of the LNA is presented. A theoretical noise figure optimization using fixed power was used as a design optimization guide. This inductively degenerated cascade topology show good noise performance which it achieve a noise figure of 1.32dB while provides a forward gain, S 21 of 18.24 dB from a 1.2V voltage supply. The input reflection coefficient, S 11 is -19 dB. © 2011 IEEE. |
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| ISSN: | |
| DOI: | 10.1109/ISIEA.2011.6108680 |