Design and analysis of 8-bit Smith Waterman based DNA sequence alignment accelerator's core on ASIC design flow

• Published in: Proceedings - UKSim 4th European Modelling Symposium on Computer Modelling and Simulation, EMS2010
• Main Author: Halim A.K.; Majid Z.A.; Mansor M.A.; Al Junid S.A.M.; Mohamed S.; Khairudin N.; Yassin A.I.M.; Idros M.F.; Hassan S.L.M.
• Format: Conference paper
• Language: English
• Published: 2010
• Online Access: https://www.scopus.com/inward/record.uri?eid=2-s2.0-79952123246&doi=10.1109%2fEMS.2010.31&partnerID=40&md5=d16b6bea9f0e1dd80176ff3fb1926877

This paper present the design and analysis of 8-bit Smith Waterman (SW) based DNA sequence alignment accelerator's core on ASIC design flow. The objective of the project is to construct and analyse the core module that can perform the Smith Waterman algorithm's operations, which are comparing, scoring and back tracing, using the technique used in [1,2] on ASIC design flow. Nowadays, the DNA and protein databases are increasing rapidly and these add new challenges to the current computing resources. New techniques, algorithms, designs, hardware and software that can maximize the computational speed, minimize the power and energy consumption, and boost the throughput need to be developed in order to meet the current and future requirements. In DNA sequence alignment process, the DNA sequences are compared using different alignment requirement techniques such as global alignment, local alignment, motif alignment and multiple sequence alignment. Moreover, there are several algorithms used to perform the sequence alignment process such as NeedlemanWunch algorithm, Smith Waterman algorithm, FASTA, BLAST and so on. For this paper, the focus is on local alignment using Smith Waterman algorithm. The design was modelled using Verflog and the functionality was verified using Xilinx and VCS. The RTL codes was mapped and synthesized to technology based logics using Design Compiler (DC). The core's layout was implemented using Place and Route tool, IC Compiler (ICC). Based on the results, the core design area was 2108.937620 um2.The maximum time constraints were 6.85 ns and 6.93 ns in ICC and PT. The minimum time constraints were 0.28 ns and 0.30 ns in ICC and PT respectively. In conclusion, the design had been successfully implemented on ASIC design flow. Moreover, the results showed that the design can be further optimized to work at faster speeds. © 2010 IEEE.